Glossary
LPDDR5X
Low-power DRAM used as unified memory in Apple Silicon, DGX Spark, and Strix Halo. High capacity and efficiency, with bandwidth below HBM and GDDR.
LPDDR5X is the low-power DRAM generation used as the shared unified memorysiliconA single physical memory pool shared by CPU and GPU, so the full capacity is usable as model memory; used by Apple Silicon, Strix Halo, and DGX Spark. Open full entry in Apple Silicon, NVIDIA’s DGX Spark, and AMD’s Strix Halo. Its advantages are capacity and efficiency: a single SoC can address hundreds of GB at a low power budget, which is how a Mac Studio reaches 512 GB usable as model memory in a quiet desktop.
The tradeoff is memory bandwidthsiliconThe rate (GB/s or TB/s) at which an accelerator reads its memory. It sets the ceiling on decode tokens/sec, since each token streams the active weights once. Open full entry . LPDDR5X runs below stacked HBMsiliconStacked DRAM used as the main memory of every modern AI accelerator, with bandwidth in TB/s rather than GB/s and capacity per stack in tens of GB. Open full entry and discrete GDDR7siliconThe graphics memory generation on 2025-era consumer and workstation GPUs such as the RTX 5090 and RTX PRO 6000. High bandwidth per board, lower capacity than HBM. Open full entry : Apple’s tiers span roughly 273 GB/s on a Mac mini to 819 GB/s on the M3 Ultra, while DGX Spark and Strix Halo sit near 256 to 273 GB/s. That bandwidth, not capacity, is what caps decode tokens/sec on these machines.
The practical read: LPDDR5X unified-memory boxes are the way to hold a large model on one device, but their decode speed tracks their bandwidth tier, so a huge model that fits can still generate slowly. Capacity and bandwidth are separate specs and both belong in the decision.