RISC-V

RISC-V is an open Instruction Set Architecture governed by a Swiss non-profit, RISC-V International. Royalty-free, no licensing fees, no single-vendor control. Anyone can build a RISC-V chip without permission. This is the foundational layer that makes "open silicon" possible at all; the other two major ISAs (x86 and ARM) are proprietary and tied to specific licensors. For the open-source AI conversation, RISC-V matters because the AI hardware stack is dominated by NVIDIA's proprietary GPU ISA on top of NVIDIA-controlled hardware. Even if the weights and runtime above are open, the silicon underneath remains a chokepoint. RISC-V is the only credible path to an open accelerator stack that does not depend on one company's goodwill. The lead bet at the AI-accelerator level is Tenstorrent, whose Wormhole and Blackhole accelerators combine RISC-V CPU cores with their Tensix tensor units. Production-ready as an ISA, yes; it ships in embedded and microcontroller chips at very high volume already. As a substrate for AI training or inference at frontier scale, not yet; the software ecosystem (compilers, optimized kernels, AI frameworks targeting it) lags NVIDIA's CUDA stack by years. SiFive is the leading commercial RISC-V CPU IP vendor; Tenstorrent is the leading RISC-V-anchored AI accelerator bet. Status: foundational, real, and slow to mature into the AI-frontier role its open-stack advocates want for it.